library verilog;
use verilog.vl_types.all;
entity ctr is
    port(
        inst            : in     vl_logic_vector(4 downto 0);
        regdst          : out    vl_logic_vector(1 downto 0);
        ext             : out    vl_logic_vector(2 downto 0);
        aluop           : out    vl_logic_vector(3 downto 0);
        regwr           : out    vl_logic;
        memrd           : out    vl_logic;
        memwr           : out    vl_logic;
        memtoreg        : out    vl_logic;
        alusrc2         : out    vl_logic;
        branch          : out    vl_logic_vector(2 downto 0);
        j               : out    vl_logic;
        jr              : out    vl_logic;
        jal             : out    vl_logic;
        createdump      : out    vl_logic;
        lbi             : out    vl_logic
    );
end ctr;
